The invention relates to an integrated circuit configuration for testing transistors having pads to which the transistors are connected.
Integrated circuits are conventionally produced on semiconductor wafers. A multiplicity of circuits, generally of the same type, are thereby arranged on one wafer. The wafer is subjected to a multiplicity of process steps in order to produce the transistors which form the circuits. After various process steps, the mechanical and electrical characteristics of the completed structures and circuits are tested. The wafer is then sawed apart, a process referred to as dicing, in which individual circuits are sawed from one another to produce individual semiconductor platelets, which are referred to as chips. The test circuit configuration which is the subject of this invention is located on the wafer between the individual chips in the scribe line, also referred to as the kerf. The transistors to be tested, which are arranged in the kerf, are accessed via connecting surfaces, which are referred to as pads. The invention also relates to such a semiconductor wafer.
It is always desirable to accommodate as many chips as possible on one wafer. It is thus desirable to keep the space between the chips as small as possible. On the other hand, it is desirable to test as many transistors as possible in order to obtain a sufficiently large number of parameters to allow an assessment that is as comprehensive as possible to be made on the quality of the wafer that has been produced. Further pads are therefore provided in order to test transistors arranged in the kerf. Since the pads are used to accommodate test probes or probe needles from automatic test equipment, they require considerably more surface area than the transistor structure to be tested. The required area increases severely disproportionately for an approximately 1:1 association between the transistors to be tested and the test pads. The desire to utilize available wafer surface area as optimally as possible for usable integrated circuits is contradictory to the need to provide as many test parameter values as possible, and thus the need for as many transistors as possible for testing.
U.S. Pat. No. 5,313,158 (European patent EP-A-0 430 372) discloses a test structure for testing integrated circuits, which is arranged in the kerf of the semiconductor wafer, between the integrated circuits to be tested. Process parameters are derived from the test structures. A multiplexing circuit is provided in order to save bonding pads for these test structures, and couples the various test structures to the same connections.
German patent DE 198 19 570 (corresponding to commonly assigned, copending application Ser. No. 09/302,649) describes a test logic which is arranged in the kerf area of the semiconductor wafer and provides test signals for the semiconductor chip adjacent to the kerf. Further control signals and the supply voltage are supplied via needles to the pads arranged on the integrated circuit.
German patent DE 198 31 563 (corresponding to commonly assigned, copending application Ser. No. 09/353,612) discloses the arrangement of pads in the kerf of a semiconductor wafer, via which test signals can be provided jointly to a number of chips.
The object of the present invention is to provide an integrated circuit configuration for testing transistors and a semiconductor wafer with such a circuit configuration, which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which occupies as small an area as possible, when in an integrated form, for as many transistors as possible to be tested.
With the above and other objects in view there is provided, in accordance with the invention, an integrated circuit configuration for testing transistors, comprising:
a first multiplicity of pads, a first further pad, a second further pad, and a third further pad;
a multiplicity of transistors to be tested, the transistors each having a control connection and a controlled path between a first connection and a second connection, and the transistors being arranged in a first row and in a second row;
each of the transistors in the first row being arranged between two respective pads of the first multiplicity of pads, and the connections of the controlled path through the transistors being connected to the two pads, and the control connections of the transistors in the first row being connected to the first further pad;
the first connections of the controlled path through the transistors in the second row being each connected to a respective one of the pads, the second connections of the controlled path through the transistors in the second row being jointly connected to the second further pad, and the control connections of the transistors in the second row being jointly connected to the third further pad.
In other words, the objects of the invention are achieved by an integrated circuit configuration for testing transistors, which comprises: a first multiplicity of pads for supplying and tapping off signals, a second multiplicity of transistors to be tested, which are arranged in at least two rows, with one of the transistors in a first row in each case being arranged between two pads and the connections of the controlled path through this transistor being connected to these two pads, and the control connections of all the transistors in the first row being connected to a first further pad, one of the connections of the controlled path through in each case one of the transistors in a second row in each case being connected to a different one of the pads, and the other one of the connections of the controlled path through these transistors being jointly connected to a second further pad, and the control connections of these transistors being jointly connected to a third further pad.
An additional row of transistors to be tested is arranged in the test circuit configuration according to the invention, and these transistors are connected to the test pads which were already present and, furthermore, require only two additional test pads, which are used jointly by these transistors.
Despite doubling the testable transistors by adding a new row of transistors to be tested, the surface area consumed increases only insignificantly since only two further test pads are required. In general, the invention is open in that any desired number of further rows with transistors to be tested are arranged in a corresponding manner. The major advantage is that already existing pads are used more than once. Since pads consume a far greater surface area than additional transistors, the additional surface area requirement is governed essentially only by the additional transistors and the jointly used additional pads. In contrast, the additional wiring complexity is actually reduced. The number of additionally provided rows of transistors to be tested may be limited by the fact that the wiring flexibility is then restricted.
According to a further aspect of the invention, a semiconductor conductor wafer contains the test circuit in the space between the commercially usable integrated circuits. This intermediate space is normally then used in order to saw the usable integrated circuit chips apart from one another, and thus to separate them from one another.
The pads are intended for having test probes from automatic test equipment placed on them, in order to introduce and tap off electrical signals. The automatic test equipment can be configured and programmed appropriately in order to allow it to interact with the test circuit structures according to the invention.
In accordance with an added feature of the invention, the pads and the further pads are arranged along a first straight line, the transistors in the first row are arranged along a second straight line extending parallel to the first straight line, and the transistors in the second row are arranged along a third straight line extending parallel to the first and the second straight lines. In other words, both the pads and the transistors in each row are aligned along respective straight lines. The row of transistors and the arrangement of pads expediently run parallel to one another.
In accordance with an additional feature of the invention, the transistors are field-effect transistors, the controlled path is a drain-source path, and the control connection is a gate connection of the field-effect transistors.
In accordance with another feature of the invention, there is provided at least one further row of further transistors each with a controlled path and a control connection, a fourth further pad, and a fifth further pad. The first connections of the controlled paths through the further transistors are each connected to a respective one of the pads, and the second connections of the controlled paths of the further transistors are jointly connected to the fourth further pad, and the control connections of the further transistors are jointly connected to the fifth further pad.
In accordance with a further feature of the invention, one of the transistors in each of the first, second, and further rows is arranged along a straight line intersecting the straight line along which the pads are arranged.
In accordance with a concomitant feature of the invention, the transistors are arranged in a matrix with rows and columns running transversely to the rows.
With the above and other objects in view there is also provided, in accordance with the invention, a semiconductor wafer, comprising at least two integrated circuits formed on the wafer, and an integrated circuit configuration for testing as outlined above arranged between the at least two integrated circuits on the wafer.
The transistors to be tested are the respective transistors of the type in the integrated circuit. If complementary MOS process technology is used for the production of the wafer, the transistors are MOS field-effect transistors. The transistors have a controlled current path, which has drain and source connections at the ends. The conduction characteristic of this current path can be controlled by a control electrode, the gate. The transistors are arranged like a matrix. This means that there are two straight-line directions along which the transistors are aligned. One of the straight lines runs parallel to the alignment of the pads, as stated above. The other straight line runs transversely with respect to this and cuts the former. The straight lines are preferably at right angles to one another, thus resulting in a matrix-like, checkerboard-like grid structure.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit configuration for testing transistors, and a semiconductor wafer having such a circuit configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.